1. Field of the Invention:
The present invention relates to a current-cell matrix type digital-to-analog converter for producing an analog signal output corresponding to a digital signal input thereto.
2. Description of the Related Art:
Conventionally, when some current matrix type digital-to-analog (D/A) converter receives an analog output from a circuit, LSI (Large Scale Integration), or the like having an offset voltage, for example, directly connected thereto without a capacitor, the D/A converter applies the analog output with an offset voltage in conformity to the offset voltage of the connected circuit for adjustment.
For example, as shown in FIG. 4, a digital communication transmitter or the like comprises a modulator 1 for generating a baseband signal; and an orthogonal modulator 2 for orthogonally modulating the baseband signal in an analog domain to output an orthogonal modulated signal. Since the modulator 1 and the orthogonal modulator 2 are composed of semiconductor integrated circuits manufactured through different processes, they can differ from each other in signal potentials which maximize the performance, such as a signal-to-noise ratio, a modulation accuracy, and the like. Therefore, baseband signals I(t) and Q(t) from the modulator 1 must be applied with offset voltages, respectively, for adjustment such that a DC level signal potential of the baseband signals I(t) and Q(t), i.e., the signal ground potential matches a signal ground potential which is optimal for the performance of the orthogonal modulator 2.
The modulator 1 applies serial-to-parallel conversion on a binary transmission data in a logic circuit 3, and further differentially encodes the resulting parallel binary transmission data which is output to signal waveform generators 4, 5 that output baseband signals I(t) and Q(t) to the orthogonal modulator 2, respectively. Here, for example, as shown in FIG. 14, the signal waveform generator 4 inputs a digital signal from a ROM (Read Only Memory) 6 to a current-cell matrix type D/A converter 910 for processing. The resulting analog signal is applied with an offset voltage in a level shifter circuit 920 to generate a baseband signal which is output through a low pass filter 7
For example, the current-cell matrix type D/A converter 910 described in Japanese Patent Application Kokai No. 9-51360 (hereinafter referred to as “patent document-1”) is connected to a level shift circuit 920, and outputs an analog signal Vout to the level shift circuit 920, as shown in FIG. 12. The level shift circuit 920 has a first signal level shifter 930 which adds a level shift voltage to the analog signal Vout to output a baseband signal Vls to which an offset voltage has been applied.
As shown in FIG. 12, the level shift circuit 920 comprises a first level shifter 930; a signal ground potential determination circuit 940 which is a first reference potential generating means; a signal center potential reference circuit 950 which is a second reference potential generating means; a second signal level shifter 960; and an operational amplifier 970. The current-cell matrix type D/A converter 910 comprises a row decoder 12, a column decoder 14, a load resistor 24, and a plurality of unit current cells 912, 914, 916, 918. The level shift circuit 920 selects a unit current cell in accordance with a 10-bit input code 102, and applies the load resistor 24 with a current flowing from the selected unit current cell to determine the potential for the analog signal Vout.
A plurality of unit current cells 912, 914, 916, 918 are each configured as shown in FIG. 13. For example, each of the unit current cells 912 outputs a predetermined output when a row decode signal and a column decode signal are both at “H.” This current value can be set by adjusting the width of a gate of a current regulating transistor 36. Also, each of the unit current cells is supplied with a bias voltage 104 input to the current-cell matrix type D/A converter 910 from the outside.
The current-cell matrix type D/A converter 910 includes (26-1) current cells 912, having a current value of I0/27, arranged on an array, and one each of the unit current cell 914 having a current value of I0/28, the unit current cell 916 having a current value of I0/29, and the unit current cell 918 having a current value of I0/210. The upper six bits of the input code 102 is D/A converted by a selected number of the unit current cells 912 having a current value of I0/27, while the lower three bits of the input code 102 are D/A converted depending on whether to select the unit current cells 914, 916, 918, the current values of which are weighted, resulting in 9-bit D/A conversion in total.
The first signal level shifter 930, which comprises a source follower circuit made up of PMOS (P-channel Metal-Oxide Semiconductor) transistors 932, 934, adds a level shift voltage to the analog signal Vout output from the current-cell matrix type D/A converter 910 in an analog domain to output the baseband signal Vls. In this event, the PMOS 932 is applied with the analog signal Vout at its gate, while the PMOS 934 is applied with an output potential Vbls from the operational amplifier 970 at its gate to output the signal Vls from the source of the PMOS 932 (drain of the PMOS 934).
The signal ground potential determination circuit 940 is comprised of a plurality of resistors 942 connected in series between a power supply and the ground, and a selector circuit 944. The selector circuit 944 selects a potential at one connection from the plurality of resistors 942 in accordance with an offset voltage adjusting signal 980 input thereto to determine a signal ground voltage Vsg as a first reference potential.
The signal center potential reference circuit 950, which is comprised of resistors 952, 954 connected in series between the power supply and ground, outputs the potential at a connection of the two resistors as a signal center potential Vm which is a second reference potential. The resistances of the resistors 952, 954 are set such that the potential Vm is equal to a center potential Vct of the analog voltage Vout output from the current-cell matrix type D/A converter 910.
The second signal level shifter 960 is identical in configuration to the first signal level shifter 930, or is designed such that a device size ratio of a PMOS transistor 962 to a PMOS transistor 964 is equal to a device size ratio of the PMOS 932 to PMOS 934, with the PMOSs 932, 934 making up the first signal level shifter 930. The PMOS 962 is applied at its gate with the signal center potential Vm from the signal center potential reference circuit 950, while the PMOS 964 is applied at its gate with the bias potential signal Vbls from the operational amplifier 970, causing a potential Vrpl to be output from the source of the PMOS 964 (drain of the PMOS 964).
For example, each of the signal waveform generators 4, 5 for supplying a baseband signal to the orthogonal modulator 2 comprises the current-cell matrix type D/A converter 910 as described above, and can adjust an the offset signal applied to the baseband signal in order to match the signal ground potential for the baseband signal with an optimal signal ground potential for the performance of the orthogonal modulator 2.
The current-cell matrix type D/A converter described in the patent document-1, which is connected to a level shift circuit, can apply and adjust the offset voltage to the analog signal.
However, a large circuit scale of the level shift circuit described in the patent document-1 results in an increase in the chip area including the current-cell matrix type D/A converter. Also, when the analog signal is differentially output from the current-cell matrix type D/A converter, two of the level shift circuits are required to cause a further increase in the circuit scale.
When the analog signal output form the current-cell matrix type D/A converter is converted to a voltage by the level shift circuit to output the baseband signal, the first signal level shifter, in particular, is affected by the voltage-current (V-I) characteristic in the transistor 12a to degrade the linearity of the output baseband signal.